Multi Gbps LDPC decoding with a single IP block
The LDPC decoding algorithm inherently facilitates parallelism in hardware FEC decoders. This, and the fact that it is the most powerful error correction algorithm known, make it the ideal choice for FEC in high speed applications. On our LDPC page we discuss our layered decoder that processes a single code macro cell at a time and handles data-rates in the region of 1Gbps. Here we present a product for several Gbps. Instead of processing a code macro cell in one cycle, this design processes one or more macro rows in a cycle. Potentially an entire decode iteration can be achieved in a single cycle. Allowing 5-10 iterations per code block, this means a code block can be decoded in 5-10 clock cycles.
Clearly the Gbps LDPC decoder is highly parallel and therefore more costly in silicon area than say a decoder used for WiFi. Cost is mitigated simply by using a relatively short code block size and a number of emerging Gbps standards are now specifying short code word lengths (e.g. 672) with highly parallel decoders in mind.
Our LDPC GIG product is designed to support high throughput for short code word length LDPC codes. Ideally the codes used for different code-rates should have some commonality in their code definitions, which helps reduce gate-count. A number of architectural options allow the single master RTL description to be synthesised to a range of throughput capabilites that allow it to efficiently support the range of 'Modulation Coding Schemes' offered by the new standards.
802.11ad may well sound WiFi related, and of course it is in many respects, however it is a PAN rather than LAN standard. It operates at very short range (1m) due to the 60GHz band that is used and can provide data-rates of >6Gbps. The LDPC code specified for this standard is relatively short (672 bits), and the macro cell size is also small (42 bits). Now if the macro cell size had been larger than that used for WiFi (81 bits) then the throughput of a 'macro cell at a time' decoder would achieve proportionately higher data-rates than WiFi, but this is not the case.
The 802.11ad macro cell size, however is only 42 bits, which is favourable for a partially/fully parallel decoder and unfavourable for a 'macro cell at a time' decoder. Our 802.11ad LDPC decoder uses our LDPC GIG architecture configured to operate at one code macro row at a time for the lower MCS (in the 1-2 Gbps region), while the highest MCS (>6Gbps) are handled with all macro rows processed in a single cycle. The architecture scaling provides sufficient range of capabilities that any MCS can be targeted with low implementation loss.
This standard is largely in the same 'space' as 802.11ad. It is also intended for short range PAN in the 60GHz band. The LDPC code has a 672 bit code word and the code is based on 21 bit macro cell. The code is eminently suitable for our LDPC GIG architecture and we would be happy to supply a solution for this standard.
802.11ac is the latest generation of WiFi. It takes WiFi (previously 802.11n) into the Gbps region using one or more 80GHz channels. Compared to 80211n, a higher proportion of the OFDM tones are used for data (as opposed to pilot symbols) and the modulation is extended to support 256QAM. This takes the data-rate for an 80MHz channel with 2 spatial streams to 866Mbps. Using 160MHz channels, or 80MHz channels with 4 spatial streams, 1.733Gbps will be achieved. 8 Spatial streams delivers 3.46Gbps. A multi-user feature allows a powerful server, say with 8 stream support, to communicate with multiple clients, allocating its streams according to the capabilities of the clients.
The LDPC code for 802.11ac is the same as 802.11n. WIth code words of 1944 bits and a macro cell size of 81 bits an application of our LDPC GIG architecture would be over powerful, delivering performance of more than 10Gbps even on the lowest performing setting. Instead we recommend a "macro cell at a time" decoding approach.
We can support 802.11ac today using our industry proven 802.11n/ac decoder. A single decoder clocked at 480MHz supports 1733Mbps, while a pair of decoders are used to support higher data-rates.
Hard Disk Drives (HDD)
Our LDPC GIG architecture is readily capable of supporting the 6-10Gbps data-rates needed for error correction on the read channel of HDDs. Typically LDPC would be used as the inner code and an outer code would be used to effectively extend the code block length. Long code blocks perform better than soft ones. For instance the 1944 bit 802.11n code has close to 1 dB of coding gain over the 648 bit 802.11n code. Clearly there are a number of alternative approaches - long code word LDPC versus short code word LDPC combined with, for example, a Reed Solomon outer decoder. Please contact us to discuss the status of our research in this area.
We have low overheads and you can generally reduce your costs by buying in our LDPC Encoder and Decoder IP for FPGA and ASIC. In addition you can reduce project timescales as the IP is already available. Support for 802.11n, 802.11ac, 802.11ad is currently available and we are happy to consider other standards. If you have an interest in a product please review the datasheet and send an email to enquiries to ask for a quotation. Once you receive a quotation you can cite the quotation in a purchase order. The quotation will list out licensing terms and you confirm acceptance of these via your purchase order. Once the purchase order is received you can download it from our ftp server.
For RTL products we offer a tiered contract that agrees prices for development, single-use and multi-use up front while allowing you to start with just a low-cost development licence.
The IP is provided with 12 months support and maintenance. The support is limited to problem resolution and not, for example integration into your system, however additional support can be provided at our consultancy rate. Please see services for further information.